Method for determining QPSK modulation sequence of a downlink synchronization code

ABSTRACT

A method is provided for determining the modulation sequence of the downlink synchronization codes. The method comprises: the method comprises a three step process: step one is to measure the phase of the downlink synchronization code. Step two is to generate an accurate of the phase of the downlink synchronization code by removing the frequency drift effect, step three is to determine whether the sequence S1 or S2 is finally detected. The method allows for high accuracy to be achieved for determination of the modulation sequence of the downlink synchronization codes.

TECHNICAL FIELD OF THE INVENTION

The present invention relates in general to mobile communication technology, and more specifically, to a method for determining the QPSK modulation sequence of consecutive SYNC-DL codes in the low chip option of Universal Mobile Telecommunication System (UMTS) Time Division Duplex (TDD) and TD-SCDMA.

DESCRIPTION OF THE RELATED ART

In a digital cellular mobile communication system, after a mobile handset is turned on, an initial cell search is performed. Some purposes of the cell search are to select a suitable working frequency and to obtain downlink synchronization between the mobile handset and a base station at the working frequency. In a cellular mobile communication system, a pilot channel generally performs the downlink synchronization. In this way, the mobile handset correctly receives a message sent by the base station.

An objective of synchronization is to be able to receive data of a broadcast channel (BCH) which is carried by a primary common control physical channel (P-CCPCH) in Timeslot 0 of a superframe. Presently, two different sequences of the so-called SYNC-DL code modulation are specified for four sequential DwPTS in a superframe. See 3GPP TS 25.223 v5.1.0 Sec. 9.1.1. A first sequence, S1, indicates that there is a P-CCPCH carrying a BCH in the next superframe; a second sequence, S2, indicates that there is no such P-CCPCH in the next superframe. Where sequence S1 of the modulation of the SYNC-DL codes of a superframe is found, the data from the BCH can be read from the P-CCPCH of the next superframe.

FIG. 1 illustrates the time frame structure for the 1.28 Mcps low clip rate option of a wireless system as currently specified by 3GPP. Ten (10) ms frames are divided into two sub-frames of five (5) ms each. Each sub-frame includes seven (7) timeslots and a separate area for uplink and downlink synchronization (SYNC) signals. Each Timeslot 0-6 is configured to receive communication data symbols and an identifying midamble code. Timeslot 0 is always a downlink (DL) slot. Timeslot 1 is always an uplink (UL) slot. Timeslots 2-6 are configurable for either UL or DL usage.

Between Timeslot 0 and Timeslot 1, there exists a ninety-six (96) chip long Downlink Pilot Timeslot (DwPTS), a ninety-six (96) chip long guard period (GP) and a one-hundred sixty (160) chip long uplink pilot timeslot (UpPTS). Within the DwPTS there is a thirty-two (32) chip long guard period and a 64 chip Synchronous (SYNC-DL) code section.

Quadrature phase shift keying (QPSK) modulation is used on the SYNC-DL codes. In each sub-frame, the midamble code in the DL Timeslot 0 provides a QSPK phase reference of the SYNC-DL code in the DwPTS. Accordingly, once the midamble code of Timeslot 0 is determined, the QPSK modulation of a SYNC-DL code in the DwPTS of the sub-frame can be ascertained.

Four consecutive phases (phase quadruple) of the SYNC-DL are used to indicate the presence of the P-CCPCH in the following 4 sub-frames. In case the presence of a P-CCPCH is indicated, the next following sub-frame is the first sub-frame of the interleaving period. As QPSK is used for the modulation of the SYNC-DL, the phases 45, 135, 225, and 315 degrees are used.

The total number of different phase quadruples is 2 (S1 and S2). A quadruple always starts with an even system frame number ((SFN mod 2)=0). Table below is showing the quadruples and their meaning. Name Phase quadruple Meaning S1 135, 45, 225, 135 There is a P-CCPCH in the next 4 sub-frames S2 315, 225, 315, 45 There is no P-CCPCH in the next 4 sub-frames

For the purpose of determining P-CCPCH position and then reading of a full BCH message, the QPSK modulation of consecutive SYNC-DL sequences needs to be detected.

A typical process for determining the phase of the QPSK modulation that is on the SYNC-DL code over multiple sub-frames is as follows: (1) measure SYNC-DL sequence phase, denoted as φ_(S), (2) generate the QPSK modulation φ of the downlink synchronization code, SYNC-DL sequences by using a decision device based on φ_(S) according to the relationship detailed below. $\begin{matrix} {\phi = \left\{ \begin{matrix} {45^{{^\circ}},} & {0^{{^\circ}} \leq \phi_{S} < 90^{{^\circ}}} \\ {135^{{^\circ}},} & {90^{{^\circ}} \leq \phi_{S} < 180^{{^\circ}}} \\ {225^{{^\circ}},} & {180^{{^\circ}} \leq \phi_{S} < 270^{{^\circ}}} \\ {315^{{^\circ}},} & {270^{{^\circ}} \leq \phi_{S} < 360^{{^\circ}}} \end{matrix} \right.} & \quad \end{matrix}$

Based on QPSK modulation φ of four or more consecutive SYNC-DL code, a decision circuit determines whether or not a selected sequence has been detected, such as the S1 sequence referenced above. When the selected modulation sequence is detected, the decision circuit identifies the start of a superframe in which BCH data is carried on the P-CCPCH in Timeslots 0. This is currently specified in 3GPP as the next superframe following an S1 sequence of modulations of the DwPTS.

The above mentioned method does not take into consideration the frequency drift between the local oscillator and that of the base station. In “real world” transmissions, carrier frequency offset is nearly impossible to avoid. Furthermore, since the SYNC-DL code is about 500 chips in length away from the midamble code in Timeslot 0, a frequency drift as small as 200 Hz can generate a corresponding phase drift up to 28°.

In view of the above mentioned problem, there is a need for a method capable of detecting the modulation sequence in an efficient and accurate manner.

SUMMARY OF THE INVENTION

The present invention discloses a method for determining the phase of QPSK modulation of the downlink synchronization code in an accurate manner by removing the frequency drift effect.

The present invention comprises of the steps of: measuring the phase of the downlink synchronization code, generating a replica of the phase of the SYNC-DL code by removing the frequency drift effect; and, determining whether the phase sequence S1 or S2 is detected.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a burst diagram illustrating the frame structure for the 1.28 Mcps option of a 3GPP system.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

While the specification concludes with claims defining the features of the invention that are regarded as novel, it is believed that the invention will be better understood from a consideration of the following description in conjunction with the drawing figures.

One embodiment of the method of detecting the modulation sequence of SYNC-DL codes can be implemented as follows: step one is to measure the phase of SYNC-DL codes φ_(S); step two is to remove the negative impact of the frequency drift by subtracting from the phase of SYNC-DL codes φ_(S) the phase drift Δφ_(S). The result is the QPSK modulation of the SYNC-DL codes which is denoted as φ. Here the phase drift Δφ_(S) is defined by the expression of Δφ_(S)≈360*Δƒ*(500/128000)≈ƒ*0.14 where Δƒ is the frequency offset between the local oscillator and that of base station and is measured in the UE receiver. Step three is detection of the appropriate modulation sequence S1 or S2. When an appropriate modulation sequence of SYNC-DL codes is detected, such as sequence S1 above, the mobile handset can then read data sent by the base station in a broadcast channel (BCH) which is carried on a P-CCPCH in the Timeslots 0 of a superframe which then enables the mobile handset to proceed with bidirectional communication with the base station which sent the BCH data.

In view of the current specified 1.28 Mcps option, another embodiment of the invention may be implemented as follows: as the duration of four or more consecutive subframes is only about 20 ms long, in such a short period, the frequency offset of the consecutive subframes can be regarded as a constant, accordingly their respective phase drift may be considered a constant. Thus, the phase difference between the two SYNC-DL codes in successive subframes can remove the impact of the frequency drift.

It is appreciated that the difference sequence for the sequence of SYNC-DL code QPSK modulation (S1 and S2) is ascertained in the system. The decision process works in the following manner:

sequence S₁ over the current four or more consecutive SYNC-DL codes is identified within the following two scenarios, one of which is when sequence S1 is detected over the previous four or more consecutive SYNC-DL code and in the meantime the sequence dS is detected as dS1_a : {0, 270, 180, 270}, another case is that a sequence S2 is identified over the previous four or more consecutive SYNC-DL codes and in the meantime the sequence dS is detected as dS1_b : {90, 270, 180, 270}.

Sequence S2 over the current four or more consecutive SYNC-DL codes is identified within the following two scenarios, one of which is when sequence S1 is detected over the previous four or more consecutive SYNC-DL code and in the meantime the sequence dS is detected as dS2_a : {180, 270, 90, 90}, another case is that a sequence S2 is identified over the previous four or more consecutive SYNC-DL codes and in the meantime the sequence dS is detected as dS2_b : {270, 270, 90, 90}.

In this embodiment, in order to identify the S1, S2 sequence, the following steps are performed: first, measure the phase of the current SYNC-DL code which is denoted as φ_(S), then compute the phase difference between φ_(S) and the former SYNC-DL code, the result is denoted as Δφ_(S), next Δφ is generated in decision device based on Δφ_(S) according to the relationship detailed below. ${\Delta\phi} = \left\{ \begin{matrix} {0^{{^\circ}},} & {{- 45^{{^\circ}}} \leq {\Delta\phi}_{S} < 45^{{^\circ}}} \\ {90^{{^\circ}},} & {45^{{^\circ}} \leq {\Delta\phi}_{S} < 135^{{^\circ}}} \\ {180^{{^\circ}},} & {135^{{^\circ}} \leq {\Delta\phi}_{S} < 225^{{^\circ}}} \\ {270^{{^\circ}},} & {225^{{^\circ}} \leq {\Delta\phi}_{S} < 315^{{^\circ}}} \end{matrix} \right.$

Thus, when the phase of the N consecutive SYNC-DL codes is measured and obtained, a sequence (denoted as dS) of Δφ of (N−1) consecutive SYNC-DL codes may be generated.

The sequence dS is input to a decision device to make a determination as to whether sequence S1 or S2 is appropriate. In the decision device, a sequence S1 over the current four or more consecutive SYNC-DL codes is identified within the following two scenarios, one of which is when sequence S1 is detected over the previous four or more consecutive SYNC-DL codes. In the meantime, the sequence dS is detected as dS1_a : {0, 270, 180, 270}. Another case is that a sequence S2 is identified over the previous four or more consecutive SYNC-DL codes and in the meantime the sequence dS is detected as dS1_b : {90, 270, 180, 270}.

In the decision device, a sequence S2 over the current four or more consecutive SYNC-DL codes is identified within the following two scenarios, one of which is when sequence S1 is detected over the previous four or more consecutive SYNC-DL code and in the meantime the sequence dS is detected as dS2_a : {180, 270, 90, 90}, another case is that a sequence S2 is identified over the previous four or more consecutive SYNC-DL codes and in the meantime the sequence dS is detected as dS2_b : {270, 270, 90, 90}.

With the present invention, it can be determined whether or not a selected sequence has been detected, such as the S1 sequence referenced above. When the selected modulation sequence is detected, superframe timing (SFT) is output to identify the start of a superframe in which BCH data is carried on the P-CCPCH in Timeslots 0. This is currently specified in 3GPP as the next superframe following an S1 sequence of modulations of the downlink synchronization code. This enables reading of a full Broadcast Channel message.

While the invention has been described in the context of a preferred embodiment, it will be apparent to those skilled in the art that the present invention may be modified in numerous ways and may assume many embodiments other than that specifically set out and described above. Accordingly, it is intended by the appended claims to cover all modifications of the invention which fall within the true spirit and scope of the invention. 

1. A method of determining the modulation sequence of the downlink synchronization codes, the method comprising: measuring the phase of a downlink synchronization code; generating an estimate of the phase of the downlink synchronization code by removing a frequency drift effect; and determining whether the sequence S1 or S2 is finally detected.
 2. The method of claim 1, wherein the estimate of the phase is provided by removing a phase compensation from the phase of the downlink synchronization code and the phase compensation is obtained based on the frequency drift which is measured in a receiver.
 3. The method of claim 1, wherein the estimate of the phase is obtained by: obtaining a sequence of phase difference of the successive downlink synchronization codes; and comparing to certain selected difference sequences to determine the phase modulation sequence of the downlink synchronization code. 